Design of an 8192-point Sequential I/O FFT Chip

This paper presents an efficient VLSI design of 8kpoint pipeline fast Fourier transform (FFT) processor capable of producing the sequential order output. The proposed FFT architecture is derived based on the modified delay feed-forward data commutator, and processes the internal dual data streams in the real and imaginary alternate approach. Compared with the general pipeline FFT designs, ours can achieve full butterfly hardware efficiency such that the required number of adders can be reduced by a half. In order to generate the sequential output order sequence, this paper also proposes an efficient reorder buffer design which can be used to replace the last stage’s commutator module for the saving of internal buffer. The FFT decomposition method for the proposed design is based on a new radix-2 × 2 FFT algorithm such that only two and a half general complex-number multipliers are used. Finally, by proper data partition and allocation, the data storage required for data commutators and the output reorder buffer can both be efficiently realized by multi-bank single-port memory modules. The proposed FFT processor has been implemented and fabricated by 0.18μm CMOS process technology. The core size is about 8.74mm. This chip is suitable for digital video broadcasting (DVB) applications not only because it can perform the sequential input/output order 8k FFT, but it also consumes low power. To satisfy the DVB throughput requirement, this chip can run under the clock rate of 8MHz and the supply voltage of 1.33V, and only dissipates 20.6 mW.